Semiconductor memory (e.g., dynamic random-access memory, DRAM) may be configured in an array which comprises an x-axis direction (i.e., row direction) and a y-axis direction (i.e., column direction). Wordlines may extend along the row direction, and bitlines may extend along the column direction.
The semiconductor memory (i.e., integrated memory) may include active regions configured as pedestals, with such pedestals being slanted relative to the x and y axes. The pedestals may be fabricated with two sets of patterns, and each set may be slanted relative to the x and y axes. If deviation in alignment between the two sets of patterns occurs, the shape of one or more of the active regions will change relative to a desired shape. This may alter performance characteristics of the altered active regions. Additionally, or alternatively, undesired alteration of the shapes of the active regions may complicate the alignment of the wordlines and/or the bitlines with the active regions.
It is desired to develop new methods for patterning components which may be slanted relative to the x and y axes of a memory array. In some applications, it is desired to develop new methods for patterning active regions of a DRAM array.